VirtualCFG::EdgeConditionKind

The conditions attached to edges are marked to determine which conditions trigger control to flow along that edge (as opposed to other edges out of the same source node). For conditional branches (except eckCaseLabel and eckDefault), the conditions are implicit and depend on knowledge of the particular control structure. Fortran support for this is underdeveloped; single AST nodes representing variable‐length loops was not part of the original design of the CFG code.

Synopsis

Declared in <SageIII/virtualCFG/virtualCFG.h>

enum EdgeConditionKind;

Members

Name	Description
eckUnconditional
eckTrue	Normal, unconditional edge
eckFalse	True case of a two‐way branch
eckCaseLabel	False case of a two‐way branch
eckDefault	Case label (constant is given by caseLabel())
eckDoConditionPassed	Default label
eckDoConditionFailed	Enter Fortran do loop body
eckForallIndicesInRange	Fortran do loop finished
eckForallIndicesNotInRange	Start testing forall mask
eckComputedGotoCaseLabel	End of forall loop
eckArithmeticIfLess	Case in computed goto ‐‐ number needs to be computed separately
eckArithmeticIfEqual	Edge for the arithmetic if expression being less than zero
eckArithmeticIfGreater	Edge for the arithmetic if expression being equal to zero
eckInterprocedural	Edge for the arithmetic if expression being greater than zero
eckError	Edge spanning two procedures

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